Equivalence Checking in Embedded Systems Design Verification using PRES+ model

In this paper we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems [1] [2]. These models encompass a broad range of styles, characteristics, and application domains and include the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this report, we have used a PRES+ model (Petri net based Representation for Embedded Systems) as an extension of classical Petri net model that captures concurrency, timing behaviour of embedded systems; it allows systems to be representative in different levels of abstraction and improves expressiveness by allowing the token to carry information [3]. This modeling formalism has a well defined semantics so that it supports a precise representation of system. As a first step, we have taken an untimed PRES+ model which captures all the features of PRES+ model except the time behaviour which have reported in earlier report. A typical synthesis flow of complex systems like VLSI circuits or embedded systems comprises several phases. Each phase transforms/refines the input behavioural specification (of the systems to be designed) with a view to optimize time and physical resources. Behavioural verification involves demonstrating the equivalence between the input behaviour and the final design which is the output of the last phase. In computational terms, it is required to show that all the computations represented by the input behavioural description, and exactly those, are captured by the output description. Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concurrency. However, there is no equivalence checking method reported in the literature for PRES+ models to the best of our knowledge. In contrast, equivalence checking of FSMD models exist [4]. Although Transformation procedure from non-pipelined version PRES+ to pipelined version PRES+ is reported [3]. As a first step, we seek to hand execute our reported algorithm on a real life example and we have to translate two versions of PRES+ models to FSMD models. The rest of the paper is organized as follows. Section 2 presents the definition of PRES+ and FSMD models. Section 3 presents Proposed algorithm for conversion from an untimed PRES+ models to an FSMD models. Section 4 presents notion of equivalence, abstraction. In this section we have also presented the working principal of an example of real life embedded systems. Section 5 verify the equivalence between initial and transformed behaviour using FSMD equivalence checking method. Finally, some future works are identified in Section 6